// Cell names have been changed in this file by netl_namemap on Mon Jan  3 04:00:13 UTC 2022
////////////////////////////////////////////////////////////////////////////// 
//
//  asic_out.v
//
//  Common output/override control logic for ASIC-side PHY ouput lines
//
//  Original Author: Chris Jones
//  Current Owner:   Behram Minwalla
//
////////////////////////////////////////////////////////////////////////////// 
//
// Copyright (C) 2011 Synopsys, Inc.  All rights reserved.
//
// SYNOPSYS CONFIDENTIAL - This is an unpublished, proprietary work of
// Synopsys, Inc., and is fully protected under copyright and trade secret
// laws.  You may not view, use, disclose, copy, or distribute this file or
// any information contained herein except pursuant to a valid written
// license agreement. It may not be used, reproduced, or disclosed to others
// except in accordance with the terms and conditions of that agreement.
//
////////////////////////////////////////////////////////////////////////////// 
//
//    Perforce Information
//    $Author: ameer $
//    $File: //dwh/up16/main/dev/pma/dig/rtl/asic_out.v $
//    $DateTime: 2013/05/16 12:52:57 $
//    $Revision: #1 $
//
////////////////////////////////////////////////////////////////////////////// 

module dwc_e12mp_phy_x4_ns_asic_out #(parameter WIDTH = 1) (
output wire [WIDTH-1:0]   asic,
input  wire [WIDTH-1:0]   phy,
input  wire               cr_ovrd,
input  wire [WIDTH-1:0]   cr_ovrd_val
);

// Simple prioritized MUX to select proper value to send to ASIC based on
// bypass mode and control register override pins
//
// hand-instantiate the last mux so that it doesn't get optimized and lose
// test coverage
    //
// creg overrides are not intended to meet any timing constraints
//
// %%SYNTH:
//   set_false_path -from $creg_clk -through [get_pins $inst/cr_ovrd]
//   set_false_path -from $creg_clk -through [get_pins $inst/cr_ovrd_val*]
//   set_false_path -from $nonscan_clks -through [get_pins $inst/byp_mux/out*] -to $scan_clks
//   set_false_path -from $scan_clks    -through [get_pins $inst/byp_mux/out*] -to $nonscan_clks
//   set_false_path -from $nonscan_clks -through [get_pins $inst/byp_mux/out*] -to $scan_clks
//   set_false_path -from $scan_clks    -through [get_pins $inst/byp_mux/out*] -to $nonscan_clks
//
dwc_e12mp_phy_x4_ns_gen_mux #(.WIDTH(WIDTH)) creg_mux (
  .out (asic),
  .sel (cr_ovrd),
  .d0  (phy),
  .d1  (cr_ovrd_val)
);

endmodule
